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Description: 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
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Size: 823296 |
Author: zhangjiefei |
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Description: 此為採用ALTERA所做的DDR 控制器(verilog)-
File/Directory Description
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\doc DDR SDRAM reference design documentation
\model Contains the verilog SDRAM model
\route Contains the Quartus 2000.05 project files a routed controller design
\simulation Contains the verilog testbench, modelsim project file, and library
\source Contains the verilog source files for the DDR SDRAM reference design
\synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
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Size: 880640 |
Author: 李志偉 |
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Description: xilinx DDR verilog 控制器-DDR verilog controller FOR XILINX
Platform: |
Size: 451584 |
Author: 陈少杰 |
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Description: 9.1 异步FIFO设计实例
9.2 DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
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Size: 3950592 |
Author: shixiaodong |
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Description: Design and implementation of High Speed Pipelined DDR SDRAM memory Controller
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Size: 772096 |
Author: JAGRUTHI M S |
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Description: Atmel (Multi-port DDR-)SDRAM Controller driver.
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Size: 1024 |
Author: gtnieber |
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Description: Header file for the Atmel DDR SDR SDRAM Controller.
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Size: 3072 |
Author: nongmaodg |
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Description: DDR SDRAM Controller Core
- has been designed for use in XILINX Virtex II FPGAs
- works with DDR SDRAM Device MT46V16M16 without changes
- may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core
- has been designed for use in XILINX Virtex II FPGAs
- works with DDR SDRAM Device MT46V16M16 without changes
- may be easily adapted to any other DDR SDRAM device
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Size: 37888 |
Author: aa |
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Description: M1671 - P4 Super North Bridge –
CPU, AGP, PCI and
Memory Controller
The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit
architecture optimized for CPU bus, DDR and AGP4X interface, the M1671 has outstanding high system performance under all
types of system operations. The M1671 also has a complete set of mobile features which makes the M1671 an ideal solution
for mobile systems.
Pdf Datasheet-M1671 - P4 Super North Bridge –
CPU, AGP, PCI and
Memory Controller
The M1671 is a high-performance, high-value North Bridge that supports all Pentium 4 processors. With internal 128-bit
architecture optimized for CPU bus, DDR and AGP4X interface, the M1671 has outstanding high system performance under all
types of system operations. The M1671 also has a complete set of mobile features which makes the M1671 an ideal solution
for mobile systems.
Pdf Datasheet
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Size: 1119232 |
Author: serge |
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Description: 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of
HSTL1 and LVTTL I/O standards
/qdr2/source/qdr2.v > Main module of the QDR memory controller
/qdr2/source/pipeline.v > Pipeline module for increasing performance
/qdr2/source/oddr_xp.v > Output DDR module
/qdr2/source/pll_qdr_sim.v > Pll module for simulation
/qdr2/source/pll_qdr_syn.v > Pll module for synthesis
/qdr2/source/magma.v- 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of
HSTL1 and LVTTL I/O standards
/qdr2/source/qdr2.v > Main module of the QDR memory controller
/qdr2/source/pipeline.v > Pipeline module for increasing performance
/qdr2/source/oddr_xp.v > Output DDR module
/qdr2/source/pll_qdr_sim.v > Pll module for simulation
/qdr2/source/pll_qdr_syn.v > Pll module for synthesis
/qdr2/source/magma.v
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Size: 16384 |
Author: liuxuemin |
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